With rapid development of semiconductor manufacturing technology, semiconductor chips are manufactured with high degree of integration to provide fast computing speed, great data storage capacity, and more functions. High integration degree of a semiconductor chip can provide semiconductor devices in the semiconductor chip with small critical dimensions (CDs).
When CDs of semiconductor devices are increasingly smaller, distance between adjacent interconnect structures become smaller. Consequently, capacitance between adjacent interconnect structures increases. Such capacitance is also known as parasitic capacitance. Parasitic capacitance may affect RC delay effect of the semiconductor devices and thus affect operating speed of the semiconductor chip along with reliability of the semiconductor devices in the semiconductor chip.
Conventional methods for solving problems due to parasitic capacitance include using materials with low dielectric constant to replace materials (e.g., silicon oxide) with high dielectric constant as an interlayer dielectric layer and/or a dielectric layer between metal layers to reduce capacitance between adjacent interconnect structures.
However, semiconductor devices formed by conventional methods still have parasitic capacitance problems. At certain points, RC delay effects may still cause slow operating speed and poor reliability of the semiconductor devices.